The present invention relates to a discharger for discharging a predetermined voltage or a core voltage (VCORE) and a semiconductor memory device including the same, and more particularly to a discharger capable of discharging a different amount of current according to temperature and a semiconductor memory device including the same.
As is well known, a dynamic random access memory (DRAM) amplifies a signal using a bit line sense amplifier in a data read operation, and uses an overdriving scheme in an initial enabling period of the bit line sense amplifier in order to improve a sensing speed.
FIG. 1 is a signal timing diagram illustrating an overdriving scheme in a conventional bit line sensing operation. An amplification process and an overdriving operation of a bit line sense amplifier will be described below with reference to FIG. 1. In general, when a bitline isolation signal BIS is activated, the cell array and the bitline sense amplifier are electrically coupled to each other. When the bitline isolation signal BIS is deactivated, the cell array and the bitline sense amplifier are electrically decoupled form each other. Moreover, when a bitline equalization signal BLEQ is activated, the bitline pair BL and /BL is precharged to the precharge voltage VBLP.
A charge sharing occurs between a cell and a precharged bit line when a word line WL of the selected memory cell is enabled. Therefore, a slight voltage difference (dV) occurs between a bit line BL and a bit line bar BLB. This period is represented by a reference numeral “102” in FIG. 1.
Thereafter, a bit line sense amplifier is enabled. The voltage difference is widened, so that the bit line BL and the bit line bar BLB are set to the levels of a core voltage VCORE and a ground voltage VSS, respectively. The bit line sense amplifier is enabled by applying voltages to driving its voltage lines RTO and SB. More specifically, the bit line sense amplifier is enabled by applying the core voltage VCORE and the ground voltage VSS to the driving voltage lines RTO and SB, and amplifies voltages applied to the bit lines BL and BLB.
As described above, the bit line sense amplifier is overdriven by applying a high voltage (generally, a power supply voltage VDD) higher than a core voltage VCORE to the driving voltage line RTO during an initial enabling period. This overdriving period is represented by a reference numeral “103” in FIG. 1. A width of the overdriving period is determined by a pulse width of an overdriving pulse.
FIG. 2 is a circuit diagram of a conventional memory core.
Referring to FIG. 2, a conventional memory core includes a bit line sense amplifier 210, a sense amplifier driver 220, and a core voltage discharger 230.
The bit line sense amplifier 210 amplifies a voltage difference between a bit line BL and a bit line bar BLB. The bit line sense amplifier 210 is a latch type amplifier having two inverters cross-coupled to each other. A power supply voltage is applied to the bit line sense amplifier 210 through driving voltage lines RTO and SB.
The sense amplifier driver 220 includes transistors T1 and T2 that are respectively turned on when control signals SAP and SAN are activated. The sense amplifier driver 220 applies a core voltage VCORE or a power supply voltage VDD to a driving voltage line RTO, and a ground voltage VSS to a driving voltage line SB. In an initial enabling period, a transistor T3 is turned on in response to an overdriving pulse VDD_ON to supply a power supply voltage VDD to the driving voltage line RTO. The period where the high voltage VDD is supplied to the driving voltage line RTO is determined by a pulse width of the overdriving pulse VDD_ON. When the initial overdriving operation is finished, the transistor T3 is turned off and a transistor 14 is turned on. Thus, a core voltage VCORE is supplied to the driving voltage line RTO so that the bit line sense amplifier 210 is driven.
When the overdriving operation is finished and the core voltage VCORE begins to be supplied to the driving voltage line RTO, a current flows into a core voltage terminal from the driving voltage line RTO by the power supply voltage VDD previously applied to the driving voltage line RTO, thereby increasing a level of the core voltage VCORE. Therefore, a core voltage discharger 230 is required which can drop the increased level of the core voltage VCORE to the original level.
FIG. 3 is a graph illustrating the core voltage VCORE increased by the overdriving operation.
In FIG. 3, ΔV1 represents an increment of the core voltage VCORE, which is increased by a current flowing into the core voltage terminal by the power supply voltage previously applied to the driving voltage line RTO. In the absence of the core voltage discharger 230, the increased core voltage VCORE is slightly discharged by a leakage current or a small transistor, which is intentionally provided in the core voltage driver so as to stabilize the level of the core voltage VCORE. Accordingly, it is difficult to maintain the level of the core voltage VCORE to a target level TARGET CORE thereby not reaching an actual level ACTUAL CORE of the core voltage VCORE. In FIG. 3, ΔV2 represents an amount of a voltage discharged by the leakage current or the small transistor. That is, in the absence of the core voltage discharger 230, the level of the core voltage VCORE is not stably maintained. Instead, the level of the core voltage VCORE increases.
FIG. 4 is a schematic circuit diagram of a conventional core voltage discharger.
Referring to FIG. 4, the conventional core voltage discharger 230 discharges a core voltage VCORE by comparing the core voltage VCORE with a reference voltage VREFC. A level of the reference voltage VREFC may be set to a level substantially equal to the core voltage VCORE or half the core voltage VCORE. FIG. 4 illustrates the case where the level of the reference voltage VREFC is half the core voltage VCORE.
A discharge enable signal DC_EN has a logic high level in synchronization with a falling edge of an overdriving pulse VDD_ON indicating an overdriving period. The core voltage discharger 230 operates during the period in which the discharge enable signal DC_EN is at the logic high level.
When the discharge enable signal DC_EN becomes the logic high level, a transistor N3 is turned on to enable the core voltage discharger 230 to perform the comparison operation. The core voltage discharger 230 compares a voltage level of a half core voltage node HFVCORE with a voltage level of a reference voltage node VREFC, which corresponds to half the target voltage of the core voltage VCORE.
The node HFVCORE has a voltage level higher than the reference voltage VREFC when the core voltage VCORE is increased by the overdriving operation. Therefore, a transistor N2 is turned on stronger than a transistor N1, and a node B has a voltage level lower than a node A. A transistor P4 is strongly turned on and a voltage of a node DC_CTRL increases. A discharge transistor N5 is turned on by the increased voltage level of the node DC_CTRL, and the voltage level of the core voltage VCORE is dropped by a current flowing from a core voltage terminal to a ground voltage terminal due to the transistor N5.
That is, when the current core voltage VCORE is higher than the target core voltage VCORE, the core voltage discharger 230 drops the level of the core voltage VCORE by discharging a current from the core voltage terminal.
A level variation of the core voltage VCORE by the discharge operation of the conventional core voltage discharger 230 will be described with reference to FIGS. 5A and 5B. Transistors P1 and P2, transistors P3 and P4 and transistors N8 and N9 are respectively formed current mirror. The transistors N6 and N7 are formed an active load. When the discharge enable signal DC_EN becomes Low, the transistors N4 is turned on to supply a ground voltage VSS to the node DC_CTRL.
FIG. 5A is a graph illustrating the level variation of the core voltage VCORE when the core voltage VCORE is excessively discharged by variation of process, voltage, and temperature (PVT). Referring to FIG. 5A, the level of the core voltage VCORE is excessively dropped due to the excessive discharge of the core voltage VCORE in an initial stage, and thus a core voltage driver again operates to increase the level of the core voltage VCORE. Therefore, a ringing phenomenon is generated to fluctuate the level of the core voltage VCORE.
FIG. 5B is a graph illustrating the level variation of the core voltage VCORE when the core voltage VCORE is not sufficiently discharged by the variation of the PVT. A target level of the core voltage VCORE is not achieved until a discharge operation of the core voltage discharger 230 is finished. In this situation, the level of the core voltage gradually increases by repeating an overdriving operation.
The core voltage may be excessively or insufficiently discharged by the temperature variation, thereby causing the problems as illustrated in FIGS. 5A and 5B. However, since the conventional core voltage discharger 230 has no temperature dependence, the core voltage is excessively or insufficiently discharged by the temperature variation.